Novel test structure for speeding a stress-induced voiding test and method of using the same

ABSTRACT

A test structure, comprising a first member having a first roughly rectangular shape, wherein the roughly rectangular shape of the first member has a first width dimension, and a first length dimension that is greater than the first width dimension; and a second member having a roughly rectangular shape, wherein the roughly rectangular shape of the second member has a second width dimension and a second length dimension that is greater than the second width dimension, wherein the second member is combined with the first member to form a roughly symmetrical cross-shaped test structure, and the test structure is used for testing stress-induced voiding.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continued application (CA) of U.S. applicationSer. No. 10/822,193 filed on Apr. 9, 2004, which is hereby incorporatedby reference.

FIELD OF THE INVENTION

The present invention relates generally to testing and diagnostics ofline processes used for the manufacture of integrated circuit devicesand more specifically to the detection and measurement of voids incopper interconnect metallurgy.

BACKGROUND OF THE INVENTION

The manufacture of large scale integrated circuits in a mass productionfacility involves hundreds of discrete processing steps beginning withthe introduction of blank semiconductor wafers at one end and recoveringthe completed chips at the other end. The manufacturing process isusually conceived as consisting of the segment wherein the semiconductordevices are formed within the silicon surface (front-end-of-line) andthe portion which includes the formation of the various layers ofinterconnection metallurgy above the silicon surface (back-end-of-line).Most of these processing steps involve depositing layers of material,patterning them by photolithographic techniques and etching away theunwanted portions. These materials consist primarily of insulators andmetal alloys.

In order to monitor the integrated circuit manufacturing process, teststructures that are representative of the circuit elements are typicallyincorporated into regions of the wafer outside of the integrated circuitchips as product failures are closely correlated to test structure/sitefailures.

Examples of these in-line test devices are: a dumb-bell structuretestable with a four point probe to establish proper resistivity of adeposited layer; or long serpentine metal lines which can be tested toestablish the presence of particulate defects by testing for electricalopens and shorts. These devices are typically designed with criticalareas much larger than their corresponding elements in the integratedcircuit so they are more sensitive to defects and can be tested atvarious stages during processing. In addition to such devices whichcharacterize the cleanliness and integrity of the process line, testsites must also be provided which can characterize the integrity ofpattern alignment and planar dimensions.

Of particular interest is this invention is the ability to detect theformation of voids in buried (copper) interconnect lines. These voidsare typically created by mechanical stresses which cause delamination ofthe metal line from the adjacent insulative matrix. The resulting void,while not directly producing an open circuit in the metal line, isnevertheless responsible for creating a hot spot when a current ispassed through the line. Such hot spots encourage electromigration inthe copper which in turn causes migration of the void along the line,eventually combining with other voids to form a larger void at a pointwhere the metal lines meet a contact or via. The result is an “open”failure. It would therefore be desirable to have a means of earlydetection of hidden stress induced voids in metal lines.

Traditional test structures use the copper (Cu) volume effect (wheremore volume causes more micro-vacancies produced after baking) todominate the SIV failure only.

U.S. Pat. No. 6,037,795 to Filippi et al. describes a multiple devicetest layout.

U.S. Pat. No. 6,191,481 to Bothra et al. describes electromigrationimpeding composite metallization lines and methods for making the same.

U.S. Pat. No. 5,973,402 to Shinriki et al. describes a metalinterconnection and a method for making the same.

U.S. Pat. No. 5,504,017 to Yue et al. describes void detection inmetallization patterns.

U.S. Pat. No. 5,156,909 to Henager, Jr. et al. describes thick,low-stress films, and coated substrates formed therefrom, and methodsfor making same.

U.S. Pat. No. 5,010,024 to Allen et al. describes passivation forintegrated circuit structures.

U.S. Pat. Nos. 6,174,743 B1 and 6,221,794 B1, both to Pangrie et al.,describe a method of reducing incidence of stress-induced voiding insemiconductor interconnect lines.

SUMMARY OF THE INVENTION

Accordingly, it is an object of one or more embodiments of the presentinvention to provide a novel test structure for speeding thestress-induced voiding test.

It has now been discovered that the above and other objects of thepresent invention may be accomplished in the following manner.Specifically, a test structure, has: (1) a first member having: aroughly a rectangular shape; a first width dimension; and a first lengthdimension that is greater than the first width dimension; and (2) asecond member having: a roughly a rectangular shape; a second widthdimension; and a second length dimension that is greater than the secondwidth dimension combined with the first member to form a roughlysymmetrical cross-shaped test structure, wherein the test structure isused for testing stress-induced voiding.

The invention further provides another test structure, comprising: afirst member having a first roughly rectangular shape, wherein theroughly rectangular shape of the first member has a first side with afirst width dimension W1, and a second side with a first lengthdimension L1 that is greater than the first width dimension W1; and asecond member having a roughly rectangular shape, wherein the roughlyrectangular shape of the second member has a third side with secondwidth dimension W2 and a fourth side with a second length dimension L2that is greater than the second width dimension W2, wherein the secondmember is combined with the first member to form a roughly symmetricalcross-shaped test structure, wherein W1 is larger than (L2-W1)/2 or(L1-W2) /2, or W2 is larger than (L2-W1)/2 or (L1-W2)/2.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from the followingdescription taken in conjunction with the accompanying drawings in whichlike reference numerals designate similar or corresponding elements,regions and portions and in which:

FIG. 1 is a top or bottom down plan view of a test structure known tothe inventor showing stress contour simulation.

FIG. 2 is a top or bottom down plan view of the preferred embodimenttest structure of the present invention showing stress contoursimulation.

FIG. 3 is a graph showing relative failure rate by length/width/length.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Structure Known to the Inventor—not to be Considered Prior Art—FIG. 1

FIG. 1 illustrates a structure known to the inventor and is not to beconsidered prior art for the purposes of this invention.

FIG. 1 illustrates a test structure 10 known to the inventor having asquare shape with the dimensions 2× by 2× that utilizes the volumeeffect to dominate the Stress-Induced Voiding (SIV) failure only.Included in FIG. 1 is a stress contour simulation using finite elementsanalysis (FEA) showing stress gradients 12, 14, 16. Two metal lines 18,20 intersect at about a 900° angle with a via 22 connecting their 18, 20intersection with the approximate center 24 of the square-shaped testpattern 10.

Test Structure of the Present Invention—FIG. 2

FIG. 2 illustrates the cross-shaped test structure 100 of the presentinvention for speeding a stress-induced voiding test.

The inventor has discovered that the cross-shaped test structure 100 ofthe present invention can not only evaluate the volume effect, but canalso utilize geometry-enhanced stress effect into consideration and thusthis cross-shaped test structure 100 allows more strict examination thanthe traditional test structure of FIG. 1 for SIV and provides for thespeeded-up testing so that the time to failure is reduced as the bakingtime may be reduced from about 500 hours for FIG. 1 to about 168 hoursfor FIG. 2 (also see below).

The cross-shaped test structure 100 may be formed on a special testwafer or on a test site or kerf on a product wafer. If formed upon atest wafer, the cross-shaped test structure 100 may be from about0.4×0.4 μm to about 100.0×100.0 μm.

The inventor has discovered that a test structure 100 having an areathat is about 75% (3/4) of the area of the square-shaped test structure10 known to the inventor and having a specific geometry, i.e.cross-shaped as shown in FIG. 2, accelerates SIV failure (Stress-inducedVoiding failure). Cross-shaped test structure 100 has a thickness ofpreferably from about 5000 to 10,000 Å and more preferably about 5000 Å.The cross-shaped test structure 100 is embedded and exposed within adielectric layer formed over the silicon wafer. In a preferredembodiment of the invention, the test structure 100 comprises a firstmember 190 having a roughly rectangular shape with a first widthdimension W1 and a first length dimension L1 that is greater than thefirst width dimension W1, and a second member 192 having a roughlyrectangular shape having a second width dimension W2 and a second lengthdimension L2 that is greater than the second width dimension W2. Thesecond member 192 is combined with the first member 190 to form aroughly symmetrical cross-shaped test structure 100. Preferably, W1 islarger than (L2-W1)/2, W1 is larger than (L1-W2)/2, W2 is larger than(L2-W1)/2, and/ or W2 is larger than (L1-W2)/2. In a preferredembodiment of the invention, the test structure 100 comprises a firstmember 190 having a roughly rectangular shape with a first widthdimension W1 and a first length dimension L1 that is greater than thefirst width dimension W1, and a second member 192 having a roughlyrectangular shape having a second width dimension W2 and a second lengthdimension L2 that is greater than the second width dimension W2. Thesecond member 192 is combined with the first member 190 to form aroughly symmetrical cross-shaped test structure 100. Preferably, W1 islarger than (L2-W1)/2, W1 is larger than (L1-W2)/2, W2 is larger than(L2-W1)/2, and/or W2 is larger than (L1-W2)/2.

Two metal lines 118, 120 intersect at about a 90° angle with a via 122connecting their 118, 120 intersection with the approximate center 124of the cross-shaped test pattern 100. Metal lines 118, 120 are formedwithin an inter-metal dielectric (IMD) layer formed over the dielectriclayer with the via 122 extending from the cross-shaped test structure100 to the metal line 118, 120 intersection. The via 122 having across-section of preferably from about 10³ to 10⁴ Å².

Simply, the test structure 100, metal lines 118, 120 and via 122 areformed in the same way as is the product metallization, that is:

forming a dielectric layer over the silicon substrate/wafer/forming

a cross-shaped damascene opening within the dielectric layer;

filling the damascene opening with a first copper layer;

planarizing, preferably by chemical mechanical polishing (CMP), thecopper layer to form the cross-shaped test structure 100;

forming an IMD layer over the planarized copper cross-shaped teststructure 100 and the dielectric layer;

forming a dual damascene opening within the IMD layer with the lower viaopening exposing a portion of the planarized cross-shaped test structure100 approximate its center 124;

filling the dual damascene opening with a second copper layer; and

planarizing, preferably by chemical mechanical polishing (CMP), thesecond copper layer to form the via 122 and metal lines 118, 120.

Metal lines 118, 120 have a thickness of preferably from about 5000 to10,000 Å and more preferably about 5000 Å. Via 122 has a length from thecross-shaped test structure 100 to the metal line 118, 120 intersectionof preferably from about 5000 to 10,000 Å and more preferably about 5000Å.

Graph of Relative Failure Rate by Length/Width/Length—FIG. 3

As shown in the graph of FIG. 3, the inventor has discovered that amaximum failure rate exits for a length (L) × width (W) × length (L) of10×20×10, i.e. a rectangular dimension of X by 2×, using actual datumpoints despite the theoretical failure rate shown by the dashed line ofFIG. 3.

Thus, the inventor combined two maximum failure X by 2× rectangularstructures to form the maximum failure cross-shaped test structure 10 ofthe present invention shown in FIG. 2 having a total area that is about75% (3/4) of the square-shaped test structure 10 known to the inventorand shown in FIG. 1.

Stress Contour Simulation Using FEA—FIG. 2

Also shown in FIG. 2, is a stress contour simulation using finiteelements analysis (FEA) showing stress gradients 112, 114, 116, 117exerting stresses 126 upon the approximate center 124 of thecross-shaped test structure 100 of the present invention proximate theconnection to the via 122. Thus, the geometry-enhanced stress effect ofthe cross-shaped test structure 100 is also taken into considerationpermitting a more strict examination of voiding.

The cross-shaped test structure 100 is thus enhances a maximum stressgradient (X by 2×).

These FEA simulations of FIGS. 1 and 2 are strictly derived from atheoretical model of the test site using parameters such as thermalexpansion coefficients and the thicknesses of the layers involved anduse “Von Mises” stresses (equivalent stress).

Testing Procedure Utilizing the Cross-Shaped Test Structure 100

The resistance of the cross-shaped test structure 100, lines 118, 120and via 122 is measured and then the entire structure 100, 118, 120, 122is baked at from about 150 to 200° C. for preferably from about greaterthan about 0 to 168 hours and more preferably about 168 hours and theresistance is again measured. Any voids formed in the cross-shaped teststructure 100 are detected by the differences in the initial andpost-baked resistance. Due to the geometry (that iscross-shaped)-enhanced stress effect as discussed above and illustratedby the stress contours in FIG. 2, the baking time can thus bedramatically reduced from about 500 hours needed for the structure ofFIG. 1 known to the inventor to establish if any product failureoccurred; to preferably from about 150 to 186 hours and more preferablyabout 168 hours for the cross-shaped test structure 100 of the presentinvention to establish if any product failure occurred.

While the written description of the present invention notes that thecross-shaped test structure 100, lines 118, 120 and via 124 are eachmore preferably comprised of copper (Cu).

ADVANTAGES OF THE PRESENT INVENTION

The advantages of one or more embodiments of the present inventioninclude:

1. a test structure permitting quicker testing for voids; and

2. reducing the baking time in the voiding test.

While particular embodiments of the present invention have beenillustrated and described, it is not intended to limit the invention,except as defined by the following claims.

1. A test structure, comprising: a first member having a first roughlyrectangular shape, wherein the roughly rectangular shape of the firstmember has a first width dimension, and a first length dimension that isgreater than the first width dimension; and a second member having aroughly rectangular shape, wherein the roughly rectangular shape of thesecond member has a second width dimension and a second length dimensionthat is greater than the second width dimension, wherein the secondmember is combined with the first member to form a roughly symmetricalcross-shaped test structure, and the test structure is used for testingstress-induced voiding.
 2. The structure of claim 1, further comprising:a first and second metal lines each having opposing ends; the first andsecond metal lines being joined at two of their respective opposing endsto form an intersection; and a via extending from the first and secondmetal line intersection to the approximate center of the cross-shapedtest structure.
 3. The structure of claim 1, wherein: the first lengthdimension of the first member is about twice as great as the first widthdimension of the first member; and the second length dimension of thesecond member is about twice as great as the second width dimension ofthe second member.
 4. The structure of claim 1, wherein the cross-shapedtest structure is comprised of copper.
 5. The structure of claim 1,wherein the cross-shaped test structure has a thickness of from about5000 to 10,000 Å.
 6. The structure of claim 1, wherein the cross-shapedtest structure 100 has a thickness of about 5000 Å.
 7. The structure ofclaim 1, wherein the cross-shaped test structure is formed on a testwafer or a test site within a product wafer.
 8. The structure of claim1, wherein the cross-shaped test structure is formed on a test wafer andthe cross-shaped test structure occupies an area of from about 0.4 by0.4 μm on the test wafer.
 9. The structure of claim 1, wherein thecross-shaped test structure is formed on a test wafer and thecross-shaped test structure occupies an area of from about 1.0 by 1.0 μmon the test wafer.
 10. A test structure, comprising: a first memberhaving a first roughly rectangular shape, wherein the roughlyrectangular shape of the first member has a first side with a firstwidth dimension W1, and a second side with a first length dimension L1that is greater than the first width dimension W1; and a second memberhaving a roughly rectangular shape, wherein the roughly rectangularshape of the second member has a third side with second width dimensionW2 and a fourth side with a second length dimension L2 that is greaterthan the second width dimension W2, wherein the second member iscombined with the first member to form a roughly symmetricalcross-shaped test structure, wherein W1 is larger than (L2-W1) /2 or(L1-W2)/2, or W2 is larger than (L2-W1)/2 or (L1-W2)/2.
 11. Thestructure of claim 10, wherein W1 is larger than (L2-W1)/2.
 12. Thestructure of claim 10, wherein W1 is larger than (L1-W2)/2.
 13. Thestructure of claim 10, wherein W2 is larger than (L2-W1)/2.
 14. Thestructure of claim 10, wherein W2 is larger than (L1-W2)/2.
 15. Thestructure of claim 10, further comprising: a first and second metallines each having opposing ends; the first and second metal lines beingjoined at two of their respective opposing ends to form an intersection;and a via extending from the first and second metal line intersection tothe approximate center of the cross-shaped test structure.
 16. Asemiconductor device, comprising: a substrate; a test structure fortesting voids in interconnects of the semiconductor device, disposedoverlying the substrate and comprising: a structure having a geometrywith smaller area than that of a square test structure, wherein the teststructure with the geometry has faster stress induced voiding failurethan the square test structure.
 17. The structure of claim 16, whereinthe test structure is substantially 75% area of the square teststructure.
 18. The structure of claim 16, wherein the test structure iscross shaped.
 19. The structure of claim 18, further comprising: a firstand second metal lines each having opposing ends; the first and secondmetal lines being joined at two of their respective opposing ends toform an intersection; and a via extending from the first and secondmetal line intersection to the approximate center of the cross-shapedtest structure.
 20. The structure of claim 18, wherein the cross-shapedtest structure is comprised of copper.